1. Field of the Invention
The present invention relates to testing of semiconductor devices, and more particularly to improving fault coverage of production test programs via establishment of a low voltage functional test screen.
2. Description of the Related Art
Semiconductor processing technology has advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as "die" or "chips") may use many functions that previously could not be implemented on a single die. It is common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today's integrated circuits and a concomitant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges in an effort to consistently provide defect-free products. Systems-on-a-chip, in particular, require a heavy investment in test development time and automated test equipment (ATE). Planning for testing must be done at the beginning of the design process.
The main goal of semiconductor test strategies is to screen out devices having functional or physical defects while establishing test limits that do not reject good devices. Many test development strategies have evolved, and often combinations of these strategies are utilized to provide a relatively high degree of fault coverage. Test development strategies include functional testing in which ATE test programs are executed. In functional testing, the device under test is stimulated by the ATE with specified inputs while the outputs are monitored to determine if they correspond with simulated logic values. Structural tests may also be utilized, and rely on a model of logical circuit faults. Structural tests sometimes begin with functional logic simulations that have been fault-graded and enhanced for higher fault coverage.
Another test development strategy, physical defect testing, involves creating specific tests designed to detect possible physical defects that can occur in an integrated circuit. Physical defect testing is useful for detecting defects that may not cause the device to fail functional or structural testing, but may lead to failure in the field. Defects in integrated circuits take many forms, some of which are test pattern sensitive. Gate oxide defects, drain-to-source current leaks (punch-through), and p-n junction current leaks (such as drain- or source-to-diffusion current leaks) tend to be pattern sensitive, while resistive shorts to ground or the power supply voltage are usually pattern insensitive. Quiescent current tests are a valuable tool in detecting such physical defects.
Generally, the result of test development is an ATE test program or test "sets" providing stimulus-response test "vectors" in the language of the ATE. The ATE test program causes the inputs of the device under test to be driven in a predetermined manner, while output pin voltages are measured and compared to stored test values. Current ATE test programs are derived mainly from the aforementioned functional and structural test development logic simulations.
Developing test programs is complicated by the fact that many different process variations can affect the device-to-device performance of integrated circuits. For example, differences in the physical properties of the metal layers used to interconnect transistors may result in disparities of propagation delays that a signal experiences when communicated over routing wires formed from the different metal layers. Often, the performance of the integrated circuitry can be dominated by propagation delays through longer metal interconnect wires rather than the basic gate delays of individual logic elements. This phenomena is exacerbated by the fact that as the width of a wire shrinks in deep submicron designs, the resistance of the wire generally increases. Process variations can also increase the resistances of the "via" structures used to couple the metal interconnect wires, also resulting in increased propagation delays. An increase in average propagation delays frequently result in a greater number of critical timing paths (e.g., signal paths in which best or worse case simulated propagation delays may approach the limits required for proper functionality). Many circuit timing problems involved such critical timing paths.
In order to avoid timing and other problems, integrated circuits are typically simulated in a software environment, using a variety of CAE tools, before the integrated circuits are actually fabricated. Such simulations function to reduce costly physical design iterations because modifications to an integrated circuit design are more readily achieved in software. Given the complexity of today's integrated circuits, accurate simulations is thus essential to a successful integrated circuit design. As noted, however, variations in the manufacturing process may cause the performance of an integrated circuit to deviate from simulated values.
Following fabrication of an integrated circuit, testing is performed to insure that the integrated circuit functions as designed. Although the integrated circuit may work functionally, it may not operate at the clock frequency at which it was designed to operate. Certain testing methodologies are employed to verify that the integrated circuit works "at speed." One such method is to test all circuitry functionally at the highest frequency at which the integrated circuit is designed to operate. At speed testing of all circuitry is typically not performed, however, because it is extremely difficult to create test patterns to verify an entire integrated circuit at the higher frequencies at which today's integrated circuits operate. Further, specialized testers are also required.
As a result, another method used to verify at speed functionality involves measuring a specified set of critical paths and assume that if these critical paths meet the timing specifications, all other paths are within a range of permissible simulation values. However, identification and measurement of critical paths is sometimes laborious.
To address such difficulties, process monitoring circuitry has been developed that resides on the integrated circuit itself. One such process monitor is the "PROCMON" cell developed by LSI Logic Corporation of Milpitas, Calif. The PROCMON circuits are analyzed during testing and their performance serves as a parametric indication of the integrity of the manufacturing process.
The PROCMON circuit utilizes the fact that in complementary metal-oxide-semiconductor (CMOS) circuits, the performance of the integrated circuit depends on the performance of both p-channel (PMOS) and n-channel (NMOS) transistors. Since the PMOS and NMOS transistors are formed at different stages of the manufacturing process, process variations at a given step may not affect the PMOS and NMOS transistors equally. The PROCMON circuitry includes short and long delay paths providing a first edge delay pulse in response to a logic level high to a logic low transition signal at the input terminal, and providing a second edge delay pulse when a logic low to logic high transition signal is provided at the same input terminal. The differences between the edge delay pulses are indicative of the relative performance of the PMOS and NMOS transistors being monitored. This difference is often quantified in terms of a "process factor" value K.
Even use of process monitor circuitry such as the PROCMON circuit, however, may not provide the desired degree of fault coverage for certain product designs. Some process variations, such as those affecting the physical properties of metal interconnections in multiple layer metallization processes, may result in failures that avoid detection by current process monitoring circuitry and typical functional test programs.